A conventional floating gate transistor 10 which is used in an EPROM cell is shown in FIG. 1. The transistor 10 includes a semiconductor substrate 14 with a drain region 18 and a source region 22 defined therein, a floating gate 26, and a control gate 30. A thin insulating film 34 is interposed between, and electrically insulates, the floating gate 26 from the control gate 30. Another thin insulating film 38 is interposed between, and electrically insulates, the floating gate 26 from the drain 18 and the source 22.
The floating gate 26 accumulates electrical charge that increases a threshold voltage level which must be supplied to the control gate 30 to generate conduction in a channel region 42 between the drain 18 and the source 22. The amount of electrical charge in the floating gate and, correspondingly, the magnitude of the threshold voltage, defines a binary memory state which may be represented by the transistor 10. A first memory state is represented when the threshold voltage is less than or equal to a predetermined magnitude and an opposite second memory state is represented when the threshold voltage exceeds the predetermined magnitude. The transistor 10 is programmed from the first memory state to the second memory state by increasing the threshold voltage of the transistor 10 to at least the level of the threshold magnitude.
The threshold voltage of the floating gate 26 is increased by supplying predetermined voltage levels to the transistor 10 which are sufficient to generate a high magnitude avalanche current within the channel region 42. High energy ("hot") electrons in the channel region 42 penetrate through the thin insulating film 38 to the floating gate 26 to increase the electrical charge in the floating gate 26, as is well known in the art. The thin insulating film 38 prevents the loss of electrical charge from the floating gate 26 after the supplied predetermined voltage levels are removed.
The memory state of the transistor 10 is determined or read by applying a predetermined read voltage to the control gate 30 and a predetermined sense voltage between the source and drain regions, 22 and 18, to sense whether the channel region 42 is conductive, indicating the first memory state, or nonconductive, indicating the second memory state. When the channel region 42 is conductive, a current flows between the source 22 and the drain 18.
Whenever the channel region 42 conducts current, such as while the memory state is read, hot electrons from the source-drain current can cross the thin insulating film 38 and change the amount of charge in the floating gate 26, which is known as a soft write effect. Consequently, over time the memory state of the transistor 10 can be erroneously changed during the normal operation of the transistor 10. The conventional solution to minimizing the soft write effect has been to limit the drain voltage to a relatively low magnitude.
To suppress the generation of hot electrons when the transistor 10 is read, the drain and source regions, 18 and 22, each include a high impurity concentration N+ type region 46 and a low impurity concentration N- type region 50, such as are disclosed in U.S. Pat. No. 5,241,498. The resistance of the N- region 50 is substantially greater than the resistance of the N+ region 46, which substantially reduces the magnitude of the avalanche current in the channel region 42. When the memory state of the transistor 10 is read, the N- region sufficiently suppresses the generation of hot electrons to minimize any soft write effect. When the transistor 10 is programmed from the first memory state to the second memory state, the N- region 50 has the undesirable effect of suppressing the generation of hot electrons in the channel region 42 which substantially increases the length of time which is required to raise the threshold voltage of the transistor 10 to the level which is indicative of the second memory state. Consequently, to enable the transistor 10 to be programmed in a reasonably fast time duration, the N- region 50 has an impurity concentration of substantially more than 1.times.10.sup.14 ions/cm.sup.2.
Some flash type electrically-programmable electrically-erasable memory (flash EEPROM) cells include a transistor which, in contrast to the EPROM transistor 10 (FIG. 1), is programmed and erased by causing electrons to tunnel in either direction between its drain and floating gate in response to predetermined voltages.
It is with respect to this and other background information that the present invention has evolved.